CD54HCT573F3A Texas Instruments Latches High Speed CMOS Logic Octal Transparent Latch with 3-State Output 20-CDIP

1. 4.5-V to 5.5-V VCCOperation
DWide Operating Temperature Range of−55°C to 125°
Balanced Propagation Delays andTransition Times
Standard Outputs Drive Up To 10 LS-TTLLoads
Significant Power Reduction Compared toLS-TTL Logic ICs
Inputs Are TTL-Voltage Compatible

2. description/ordering information

The ’HCT573 devices are octal transparent D type latches. When the latch-enable (LE) inputis high, the Q outputs follow the data (D) inputs.When LE is low, the Q outputs are latched at thelogic levels of the D inputs.A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (highor low) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus linessignificantly. The high-impedance state and increased drive provide the capability to drive bus lines withoutinterface or pullup components.OE does not affect the internal operations of the latches. Old data can be retained or new data can be enteredwhile the outputs are in the high-impedance state.To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullupresistor; the minimum value of the resistor is determined by the current-sinking capability of the driver

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